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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 1997-2006, zarlink semiconductor inc. all rights reserved. features ? compatible with: ? british telecom (bt) sin227 & sin242 ? u.k.?s cable communications association (cca) specification tw/p&e/312 ? bellcore gr-30-core (formerly known as tr-nwt-000030) & sr-tsv-002476 ? bellcore "cpe alerting signal (cas)" and bt "idle state tone alert signal" detection ? ring and line reversal detection ? 1200 baud bell 202 and ccitt v.23 frequency shift keying (fsk) demodulation ? 3 or 5 v 10% supply voltage ? high input sensitivity (-40 dbv tone and fsk detection) ? selectable 3-wire data interface (microcontroller or mt88e43 controlled) ? low power cmos with powerdown mode ? input gain adjustable amplifier ? carrier detect status output ? uses 3.58 mhz crystal applications ? bt calling line identity presentation (clip), cca clip, and bellcore calling identity delivery (cid) systems ? feature phones, including analog display services interface (adsi) phones ? phone set adjunct boxes ? fax and answering machines ? database query and computer telephony integration (cti) systems description the mt88e43 calling number identification circuit 2 (ecnic2) is a low power cmos integrated circuit intended for receiving physical layer signals transmitted according to bt (british telecom) sin227 & sin242, the u.k.?s cca (cable communications association) tw/p&e/312 and bellcore gr-30-core & sr-tsv-002476 specifications. the mt88e43 is suitable for applications using a fixed voltage power source between 3 and 5 v 10%. april 2006 ordering information mt88e43be 24 pin pdip tubes mt88e43bs 24 pin soic tubes mt88e43bsr 24 pin soic tape & reel mt88e43bs1 24 pin soic* tubes MT88E43BSR1 24 pin soic* tape & reel *pb free matte tin -40 c to +85 c cmos mt88e43b extended voltage calling number identification circuit 2 data sheet figure 1 - functional block diagram + - anti-alias filter fsk bandpass filter fsk demodulator data timing recovery carrier detector alert signal high tone filter alert signal low tone filter tone detection algorithm bias generator oscillator guard time std st/gt est trigout trigrc trigin data dr dclk mode fsken cd cap oscin oscout in+ in- gs vref int pwdn vdd vss to internal to internal cct. cct. interrupt generator
mt88e43b data sheet 2 zarlink semiconductor inc. figure 2 - pin connections pin description pin # name description 1in+ non-inverting input of the internal opamp. 2in- inverting input of the internal opamp. 3gs gain select (output) of internal opamp. the opamp?s gain should be set according to the nominal vdd of the application usi ng the information in figure 10. 4v ref reference voltage (output) . nominally v dd /2 . it is used to bias the input opamp. 5cap capacitor . a 0.1 f decoupling capacitor should be connected across this pin and v ss . 6trigin trigger input . schmitt trigger buffer input. used for line reversal and ring detection. 7trigrc trigger rc (open drain output/schmitt input) . used to set the (rc) time interval from trigin going low to trigout going high. an external resistor connected to v dd and capacitor connected to v ss determine the duration of the (rc) time interval. 8trigout trigger out (cmos output). schmitt trigger buffer output. us ed to indicate detection of line reversal and/or ringing. 9 mode 3-wire interface: mode select (cmos input) . when low, selects interface mode 0. when high, selects interface mode 1. see pin 16 (dclk) description to understand how mode affects the dclk pin. 10 oscin oscillator input . a 3.579545 mhz crystal should be connected between this pin and oscout. it may also be driven directly from an external clock source. 11 oscout oscillator output . a 3.579545 mhz crystal should be connected between this pin and oscin. when oscin is driven by an external clock, this pin should be left open. 12 v ss power supply ground . 13 ic internal connection . must be connected to v ss for normal operation. 14 pwdn power down (schmitt input) . active high. when high, the devi ce consumes minimal power by disabling all functionality except trigin, trigrc and trigout . must be pulled low for device operation. 15 fsken fsk enable (cmos input) . must be high for fsk demodulation. this pin should be set low to prevent the fsk demodulator from reacting to extraneous signals (such as speech, alert signal and dtmf which are all in the same frequency band as fsk). 16 dclk 3-wire interface: data clock (cmos input/output) . in mode 0 (mode pin low), this pin is an output. in mode 1 (mode pin high), this pin is an input. vdd st/gt est std int dr data dclk fsken pwdn ic cd in+ in- gs vref cap trigin trigrc trigout oscin oscout vss mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17
mt88e43b data sheet 3 zarlink semiconductor inc. the mt88e43 provides all the features and functions of fered by zarlink?s mt8841 (cnic), including 1200 baud bell 202 and ccitt v.23 fsk demodulation. th e 3-wire serial data interface provided by cnic has been enhanced to operate in two modes. in the cnic compatible mode data tr ansfer is initiated by the device. a second mode allows a microcontroller to extract 8-bit data words from the device. furthermore, the mt88e43 offers idle state tone alert signal and line reversal detection capability for bt?s cl ip, ring burst detection for the u.k.?s cca?s clip, and ring and cas detection for bellcore?s cid. functional overview the mt88e43, extended voltage calling num ber identification circuit 2 (ecnic2) is a device compatible with bt, the u.k.?s cca and bellcore specifications. as shown in figure 1, the mt88e43 prov ides an fsk demodulator as well as a 3-wire serial interface sim ilar to that of it?s predecessor, the mt8841 (cnic). the 3-wire interface has been enhanced to provide two modes of operation - a mode wher eby data transfer is initiated by the device and a mode whereby data transfer is initia ted by an external microcontroller. in addition to supporting all the feat ures and functions of the mt8841, t he mt88e43 also provides line reversal detection, ring detection and dual to ne alert signal/cas detection. these ne w functions eliminate some external circuitry previously required with the mt8841. the mt88e43 is compatible with the caller identity s pecifications of bt, the u.k.?s cca, and bellcore. bt specifications sin227 and sin242 describe the signalling mechanism between the network and the terminal equipment (te) for the caller display service (cds). cds provides calling line identity presentation (clip), which delivers to an on hook (idle state) te the identity of an incoming caller before the first ring. an incoming cds call is indicated by a polarity reversal on the a and b wires (see figure 3), followed by an idle state tone alert signal. caller id fsk information is t hen transmitted in ccitt v.23 format. mt88e43 can detect the line reversal, tone aler t signal, and demodulate the incoming ccitt v.23 fsk signals. 17 data 3-wire interface: data (cmos output) . in mode 0 data appears at the pin once demodulated. in mode 1 data is shifted out on the risi ng edge of the microcontroller supplied dclk. 18 dr 3-wire interface: data ready (cmos output) . active low. in mode 0 this output goes low after the last dclk pulse of each data word. this identifies the 8-bit wo rd boundary on the serial output stream. typically, dr is used to latch 8-bit words from a serial-to-parallel converter into a microcontroller. in mode 1 this pin will signal the availability of data. 19 cd carrier detect (cmos output) . active low. a logic low indica tes the presence of in-band signal at the output of the fsk bandpass filter. 20 int interrupt (open drain output) . active low. it is active when trigout or dr is low, or std is high. this output stays low until all three signals have become inactive. 21 std dual tone alert signal delayed steering output (cmos output) . when high, it indicates that a guard time qualified al ert signal has been detected. 22 est dual tone alert signal early steering output (cmos output) . alert signal detection output. used in conjunction with st/gt and external ci rcuitry to implement the detect and non-detect guard times. 23 st/gt dual tone alert signal steering input/g uard time (analog input/cmos output) . a voltage greater than v tgt (see figure 4) at the st/gt pin causes the device to indicate that a dual tone has been detected by asserting std high. a voltage less than v tgt frees the device to accept a new dual tone. 24 v dd positive power supply . pin description pin # name description
mt88e43b data sheet 4 zarlink semiconductor inc. the u.k.?s cca specification tw/p&e/ 312 proposes an alternate cds te interface. according to tw/p&e/312, data is transmitted after a single burst of ringing rather than before the first ringing cycle (as specified in the bt standards). the idle state tone alert si gnal is not required as it is replaced by a single ring burst. mt88e43 has the capability to detect the ring burst. it can also demodul ate either bell-202 or ccitt v.23 fsk data following the ring burst. the u.k.?s cca specifies that dat a can be transmitted in either format. bellcore specification gr-30-core is the generic requ irement for transmitting asynchronous voiceband data to customer premises equipment (cpe). another bellc ore specification sr-tsv -002476 describes the same requirements from the cpe?s perspec tive. the data transmission techni que specified in both documents is applicable in a variety of services like calling number delivery (cnd), calling name delivery (cnam) and calling identity delivery on call waiting (cidcw ) - services promoted by bellcore. in cnd/cnam service, information about a calling party is embedded in the silent interval between the first and second ring burst. the mt88e43 detects the first ring bur st and can then be setup to receive and demodulate the incoming bell-202 fsk data. the dev ice will output the demodulated data onto a 3-wire serial interface. in cidcw service, information about an incoming caller is sent to the subscriber, while he/she is engaged in another call. a cpe alerting signal (c as) indicates the arrival of cidcw in formation. the mt88e43 can detect the alert signal and then be setup to demodulate incoming fsk data containing cidcw information. functional description detection of clip/cid call arrival indicators the circuit in figure 3 illustrates the relationship between the trigin, trigrc and trigout signals. typically, the three pin combination is used to detect an event indi cated by an increase of the trigin voltage from v ss to above the schmitt trigger high going threshold v t+ (see dc electrical characteristics). figure 3 shows a circuit to detect any one of three clip/c id call arrival indicators: line reversal, ring burst and ringing. figure 3 - circuit to detect line reversal, ring burst and ringing tip/a c1=100nf r1=499k ring/b c2=100nf r2=499k mt88e43 trigout to microcontroller r3=200k r4=301k r5=150k c3=220nf trigrc trigin v dd v1 v2 v3 v4 max v t+ = 0.68 v dd min v t+ = 0.48 v dd the application circuit must ensure that, v trigin >max v t+ where max v t+ =3.74v @v dd =5.5v. tolerance to noise between a/b and v ss is: max v noise = (min v t+ )/0.30+0.7 =5.6vrms @4.5v v dd where min v t+ = 2.16v @v dd =4.5v. suggested r 5 c 3 component values: r5 from 10k ? to 500k ? c3 from 47nf to 0.68 f an example is c3=220nf, r5=150k ? ; trigout low from 21.6ms to 37.6ms after trigin signal stops triggering the circuit. notes: to determine values for c3 and r5: r5c3=-t / ln(1-v trigrc /v dd )
mt88e43b data sheet 5 zarlink semiconductor inc. 1. line reversal detection line reversal, or polarity reversal on the a and b wires indi cates the arrival of an incomi ng cds call, as specified in sin227. when the event (line reversal) occurs, trig in rises past the high going schmitt threshold v t+ and trigout , which is normally high, is pulled low. when the event is over, trigin falls back to below the low going schmitt threshold v t- and trigout returns high. the components r5 and c3 (see figure 3) at trigrc ensure a minimum trigout low interval. in a te designed for clip, the trigout high to low transition may be used to interrupt or wake-up the microcontroller. the controller can thus be put into power-down mode to conserve power in a battery operated te. 2. ring burst detection cca does not support the dual tone alert signal (refer to dual tone alert signal detection section). instead, cca requires that the te be able to detect a single burst of ringing (duration 200-450 ms) th at precedes clip fsk data. the ring burst may vary from 30 to 75 vrms and is approximately 25 hz. again in a te designed for cca clip, the trigout high to low transition may be used to interrupt or wake-up the microcontroller. the controller can thus be put into power-down mode to conserve power in a battery operated te. 3. ring detection in bellcore?s cnd/cnam scheme, the cid fsk data is tr ansmitted between the first and second ringing cycles. the circuit in figure 3 will generate a ring envelope signal (active low) at trigout for a ring voltage of at least 40 vrms. r5 and c3 filter the ring sig nal to provide an envelope output. the diode bridge shown in figure 3 works for both single e nded and balanced ringing. a fr action of the ring voltage is applied to the trigin input. when the voltage at tr igin is above the schmitt trigger high going threshold v t+ , trigrc is pulled low as c3 discharges. trigout stays low as long as the c3 voltage stays below the minimum v t+ . in a cpe designed for cnd/cnam, the trigout high to low transition may be us ed to interrupt or wake-up the microcontroller. the controller can thus be put into power-down mode to conserve power. if precise ring duration determination is critical, capacitor c3 in figure 3 may be removed. the microcontroller will now be able to time the ring duration directly. the result will be that trigout will be low only as long as the ringing signal is present. previously the rc time constant would cause only one interrupt. dual tone alert signal detection the bt on hook (idle state) caller id scheme uses a dual tone alert signal whose charac teristics are shown in table 1. bellcore specifies a similar dual tone alert signal ca lled cpe alerting signal (cas) for use in off-hook data transmission (see table 1). bellcore states that the cpe should be able to detect the cas in the presence of near end speech. the cas detector should also be imm une to imitation from near and far end speech. in the mt88e43 the dual tone alert signal is separated into a high and a low tone by two bandpass filters. a detection algorithm examines the two filter outputs to determine the presenc e of a dual tone alert signal. the est pin goes high when both tones are present. note that est is only a preliminary indica tion. the indication must be sustained over the tone present guard time to be cons idered valid. tone present and tone absent guard times can be implemented with external rc components. the tone present guard time rejects signals of insufficient duration. the tone absent guard time masks momentary detection dropout once the present guar d time has been satisfied. std is the guard time qualified detector output.
mt88e43b data sheet 6 zarlink semiconductor inc. dual tone detection guard time when the dual tone alert signal is detected by the mt88e43, est goes high. when the alerting signal ceases to be detected, est goes low. the est pin signals raw detection of cas/alerting tones. since both bellc ore and bt applications require a minimum duration for valid signals, est detection must be guard time qualified. the std pin provides guard time qualified cas/alerting tone detection. when the mt88e43 is used in a call er identity system, std indicates correct cas/alerting tone detection. figure 4 shows the relationship between the st/gt, est an d std pins. it also shows the operation of a guard time circuit. the total recognition time is t rec = t gp + t dp , where t gp is the tone present guard time and t dp is the tone present detect time (refer to timing between est, st/gt and std in figures 17 and 20). the total tone absent time is t abs = t ga + t da , where t ga is the tone absent guard time and t da is the tone absent detect time (refer to timing between est, st/gt and std in figures 17 and 20). item bt bellcore low tone frequency 2130hz 1.1% 2130hz 0.5% high tone frequency 2750hz 1.1% 2750hz 0.5% received signal level -2dbv to -40dbv per tone on-hook 1 (0.22dbm 2 to -37.78dbm) 1. in the future bt may specify the off-hook signal level as -15 dbm to -34 dbm per tone for bt cidcw. 2. the signal power is expressed in dbm referenced to 600 ohm at the cpe a/b (tip/ring) interface. -14dbm b to - 32dbm per tone off-hook signal reject level -46dbv (-43.78dbm) -45dbm signal level differential (twist) up to 7db up to 6db unwanted signals <= -20db (300-3400hz) <= -7dbm asl 3 near end speech 3. asl = active speech level expressed in dbm referenced to 600 ohm at the cpe tip/ring interface. the level is measured according to method b of recommendation p.56 "objective measurement of active speech level" published in the ccitt blue book, volume v "telephone transmission quality" 1989. epl (equivalent peak level) = asl+11.7 db duration 88ms to 110ms 4 4. sin227 suggests that the recognition time should be not less than 20 ms if both tones are detected. 75ms to 85ms speech present no yes table 1 - dual tone alert signal characteristics
mt88e43b data sheet 7 zarlink semiconductor inc. bellcore states that it is desirable to be able to turn of f cas detection for an off-hook capable cpe. the disable switch allows the subscriber who disconnects a service that relies on cas detection (e.g., cidcw) but retains the cpe, to turn off the detector and not be bothered by false detection. when sw1 in figure 4 is in the b posit ion the guard time circuit is disabl ed. the detector will still process cas/alerting tones but the mt88e43 will not signal their pr esence by ensuring std is low. bt specifies that the idle state tone al ert signal recognition time should not be less than 20 ms when both tones are used for detection. that is, both t ones must be detected together for at least 20 ms before the signal can be declared valid. this requirement can be met by setting the t gp (refer to figure 5) to at least 20 ms. bt also specifies that the te is required to apply a d.c. wetting pulse and an ac load 15-25 ms after the end of the alerting signal. if t abs =t da +t ga is 15 to 25 ms, the d.c. current wetting pulse and the a.c. load can both be applied at the falling edge of std. the maximum t da is 8ms so t ga should be 15-17 ms. therefore, t gp must be greater than t ga . figure 5(a) shows a possible implementation. th e values in figures 9 and 11 (r2=r3=422k, c=0.1 f) will meet the bt timing requirements. figure 4 - guard time circuit operation + - v tgt est st/gt v dd std = v ss tones detected from c r q1 q2 mt88e43 comparator p n v ss sw1 b a detector
mt88e43b data sheet 8 zarlink semiconductor inc. figure 5 - guard time circuits with unequal times input configuration the mt88e43 provides an input arrangement comprised of an operational amplifier and a bias source (v ref ); which is used to bias the opamp inputs at v dd /2 . the feedback resistor at the opamp output (gs) can be used to adjust the gain. in a single-ended co nfiguration, the opamp is connected as shown in figur e 6. for a differential input configuration, figure 7 show s the necessary connections. figure 6 - single-ended input configuration (b) t gp < t ga t gp = r p c ln [v dd -v d (r p /r2))/(v dd -v tgt -v d (r p /r2))] t ga = r1c ln (v dd /v tgt ) r p = r1r2/(r1+r2) (a) t gp > t ga t gp = r1c ln [v dd /(v dd -v tgt )] t ga = r p c ln [(v dd -v d (r p /r2))/(v tgt -v d (r p /r2))] r p = r1r2/(r1+r2) mt88e43 v dd st/gt est r1 r2 c v dd st/gt est r1 r2 c mt88e43 v d =diode forward voltage v d =diode forward voltage c r in in+ in- gs v ref voltage gain (a v ) = r f / r in r f
mt88e43b data sheet 9 zarlink semiconductor inc. figure 7 - differential input configuration fsk demodulation the mt88e43 first bandpass filters a nd then demodulates the incoming fsk signal. the carrier detector provides an indication of the presence of sig nal at the bandpass filt er output. the mt88e43?s dual mode 3-wire interface allows convenient extraction of the 8-bit data words in the demodulated fsk bit stream. note that signals such as dual tone alert signal, speech and dtmf tones lie in the same frequency band as fsk. they will, therefore, be de modulated and as a result, fa lse data will be generated. to avoid demodulat ion of false data, an fsken pin is provided so that the fsk dem odulator may be disabled when fsk signal is not expected. there are two events that if either is true, s hould be used to disable fsken. the events are cd returning high or receiving all the data indicated by the message length word. item bt bellcore mark frequency (logic 1) 1 3 0 0 h z 1.5% 1 2 0 0 h z 1% space frequency (logic 0) 2 1 0 0 h z 1.5% 2 2 0 0 h z 1% received signal level - mark -8dbv to -40dbv (-5.78dbm to -37.78dbm) -12dbm 1 t o -32dbm received signal level - space -8dbv to -40dbv -12dbm to -36dbm table 2 - fsk characteristics c1 r1 c2 r4 r3 r2 r5 in+ in- gs v ref differential input amplifier c1 = c2 r1 = r4 (for unity gain r5= r4) r3 = (r2r5) / (r2 + r5) voltage gain (a v diff) = r5/r1 (see figure 9,10,11) input impedance (z in diff) = 2 r1 2 + (1/ c) 2
mt88e43b data sheet 10 zarlink semiconductor inc. the fsk characteristics described in table 2 are listed in bt and bellcore specifications. the bt signal frequencies correspond to ccitt v.23. the bellcore frequencies correspo nd to bell 202. the u.k.?s cca requires that the te be able to receive both ccitt v.23 and bell 202, as specif ied in the bt and bellcore specifications. the mt88e43 is compatible with both form ats without any adjustment. ? 3-wire user interface the mt88e43 provides a powerful dual mode 3-wire interface so that the 8-bit data words in the demodulated fsk bit stream can be extracted without the need either for an external uart or for the te/cpe?s microcontroller to perform the uart function in software. the interfac e is specifically designed for the 1200 baud rate and is comprised of the data, dclk (data clock) and dr (data ready) pins. two modes (modes 0 and 1) are selectable via control of the device?s mode pin: in mode 0, data trans fer is initiated by the mt88e43; in mode 1, data transfer is initiated by the external microcontroller. mode 0 this mode is selected when the mode pin is low. it is the mt8841 compatible mode where data transfer is initiated by the device. in this mode, the mt88e43 receives the fsk signal, dem odulates it, and outputs the data directly to the data pin (refer to figure 14). for each received stop and star t bit sequence, the mt88e43 outputs a fixed frequency clock string of 8 pulses at the dclk pin. each clock rising edge occurs in the centre of each data bit cell. dclk is not generated for the stop and start bits. consequently, dclk will clock only valid data into a peripheral device such as a serial to parallel shift r egister or a micro-controller. the mt88e43 al so outputs an end of word pulse (data ready) on the dr pin. the data ready signal indicates the reception of every 10-bit word (including start and stop bits) sent from the network to the te/cpe. this dr signal can be used to interrupt a micro-controller. dr can also cause a serial to parallel converter to parallel load its data into a microcontroller. the mode 0 data pin can also be connected to a personal computer?s serial communication port afte r converting from cmos to rs-232 voltage levels. mode 1 this mode is selected when the mode pin is high. in th is mode, the microcontroller supplies read pulses (dclk) to shift the 8-bit data words out of the mt88e43, onto the data pin. the mt88e43 asserts dr to denote the word boundary and indicate to the microprocessor that a new word has become available (refer to figure 16). signal level differential (twist) up to 6db up to 10db 2 unwanted signals <= -20db (300-3400hz) <= -25db (0-4khz) 3 transmission rate 1200 baud 1% 1200 baud 1% word format 1 start bit (logic 0), 8 bit word (lsb first), 1 to 10 stop bits (logic 1) 1 start bit (logic 0), 8 bit word (lsb first), 1 stop bit (logic 1) 4 1. the signal power is expressed in dbm referenced to 600 ohm at the cpe tip/ring (a/b) interface. 2. sr-3004,issue 2, january 1995. 3. the frequency range is specified in gr-30-core. 4. up to 20 marks may be inserted in specific places in a single or multiple data message. item bt bellcore table 2 - fsk characteristics
mt88e43b data sheet 11 zarlink semiconductor inc. internal to the mt88e43, the demodulated data bits are sampled and stored. afte r the 8th bit, the word is parallel loaded into an 8 bit shift register and dr goes low. the shift register?s content s are shifted out to the data pin on the supplied dclk?s rising edge in the order they were received. if dclk begins while dr is low, dr will return to high upon the first dclk. this feat ure allows the associated interrupt (see section on "interrupt") to be cl eared by the first read pulse. otherwise dr is low for half a nominal bit time (1/2400 sec). after the last bit has been read, additional dclks are ignored. ? carrier detect the carrier detector provides an indica tion of the presence of a signal in the fsk frequency band. it detects the presence of a signal of sufficient ampl itude at the output of the fsk bandpass filter. the signal is qualified by a digital algorithm before the cd output is set low to indicate carrier detecti on. an 8ms hysteresis is provided to allow for momentary signal drop out once cd has been activated. cd is released when there is no activity at the fsk bandpass filter output for 8 ms. when cd is inactive (high), the raw output of the demodulator is ignored by the dat a timing recovery circuit (refer to figure 1). in mode 0, the data pin is forced high. no dclk or dr signal is generated. in mode 1, the internal shift register is not updated. no dr is generated. if dclk is clocked (in mode 1), data is undefined. note that signals such as dual tone alert signal, speech and dtmf tones also lie in the fsk frequency band and the carrier detector may be activated by these signals . the signals will be demodulat ed and presented as data. to avoid false data detection, the fsken pin should be us ed to disable the fsk demodulator when no fsk signal is expected. ringing, on the other hand, does not pose a problem as it is ignored by the carrier detector. interrupt to facilitate interfacing with microcontrollers running in terrupt driven firmwear, an open drain interrupt output int is provided. int is asserted when trigout is low, std is high, or dr is low. when int is asserted, these signals should be read (through an input port of the microcontro ller) to determine the cause of the interrupt (trigout , std or dr ) so that the appropriate response can be made. when system power is first applied, trigout will be low because capacitor c3 at trigrc (see figure 3) has no initial charge. this will resu lt in an interrupt upon power up. also when system power is firs t applied and the pwdn pin is low, an interrupt will occur due to std. since there is no charge across the capacitor at the st/gt pin in figure 4, std will be high triggering an inte rrupt. the interrupts will not clear until both capacitors are charged. the microcontroller should ignore inte rrupt from these sources on initial power up until there is sufficient time to charge the capacitors. it is possible to clear std and its interrupt by asserting pwdn immediately after system power up. when pwdn is high, std is low. pwdn will also force both est and the compar ator output low, q2 will turn on so that the capacitor at the st/gt pin charges up quickly (refer to figure 4). power down mode for applications requiring reduced power consumption, the mt88e43 can be powered up only when it is required, that is, upon detection of one of three clip/cid call arrival indicators: line reversal, ring burst and ringing. the mt88e43 is powered down by asserting the pwdn pin. in powerdown mode, the cryst al oscillator, opamp and all internal circuitry, except for trigin, trigrc and trigout pins, are disabled. the three trig pins are not affected by power down, such that, the mt88e43 can sti ll react to call arrival indicators. the mt88e43 can be powered up by grounding the pwdn pin.
mt88e43b data sheet 12 zarlink semiconductor inc. crystal oscillator the mt88e43 requires a 3.579545mhz crystal oscillator as the master timing source. figure 8 - common crystal connection the crystal specificat ion is as follows: frequency: 3.579545 mhz frequency tolerance: 0.1%(-40 o c+85 o c) resonance mode : parallel load capacitance: 18 pf maximum series resistance : 150 ohms maximum drive level (mw): 2 mw e.g., cts mp036s any number of mt88e43 devices can be connected as show n in figure 8 such that on ly one crystal is required. the connection between osc2 and osc1 can be d.c. coupled as shown, or the osc1 input on al l devices can be driven from a cmos buffer (dc coupled) with the osc2 outputs left unconnected. to meet bt and bellcore requirements for proper tone detection the crystal must have a frequency tolerance of 0.1%. vref and cap inputs v ref is the output of a low impedance voltage source equal to v dd/2 and is used to bias the input opamp. a 0.1 f capacitor is required between cap and v ss to eliminate noise on v ref. osc1 osc2 osc1 osc2 osc1 osc2 3.579545 mhz mt88e43 mt88e43 mt88e43 to the next mt88e43
mt88e43b data sheet 13 zarlink semiconductor inc. figure 9 - application circuit application circuits the circuits shown in figures 9 and 11 are applicat ion circuits for the mt88e43. as supply voltage (v dd ) is decreased, the threshold of the device?s tone and fsk de tectors will be reduced. therefore, to meet the bt or bellcore tone reject level requirements the gain of the in ternal opamp should be reduced according to the graph in figure 10. for example when v dd =5v (+/- 10%), r 1 should equal 430 k ? and r 4 should equal 34 k ? ; and if v dd =3v (+/- 10%) r 1 should equal 620 k ? and r 4 should equal 63.4 k ? . resistors r 1 and r 4 are shown in figures 9 and 11. the circuit shown in figure 9 illustrates the use of the mt88e43 in a proprietary system that doesn?t need to meet fcc, doc, and ul approvals. it should be noted that if glitches on the tip/ring interfac e are of sufficient amplitude, the circuit will falsely detect these signals as ringing or line reversal. the circuit shown in figure 11 will provide common mode re jection of signals received by the ringing circuit. this circuit should pass safety related tests specified by fcc pa rt 68, doc cs-03, ul 1459, and csa c22.2. these safety tests will simulate high voltage faults that may occu r on the line. the circuit provi des isolation from these high voltage faults via r1 and the 12 k1 ? resistors as well as the 22 nf & 330 nf capacitors. irc manufactures a resistor (part number gs3) that should be used for r1. this resistor is a 3 w, 5%, 1 kv power resistor. the 12 k1 resistor is manufactured by irc (part number fa8425f). this resistor is a 1.5 w, 5%, fuseable type resistor. the 22 nf and 330 nf capacitors have a 400 v rating. see the application note "msan-164: applications of t he mt8843 calling number identification circuit 2" for information on designing the mt88e43 into cid and cidcw systems. in+ in- gs v ref trigin trigrc trigout mode oscin oscout v ss v dd st/gt est std int dr data dclk fsken pwdn ic mt88e43 cap cd (fsk interface mode 0 selected) vdd = to microcontroller = from microcontroller 100nf tip / a ring / b vdd vdd vdd 53k6 60k4 464k 499k, 5% 499k, 5% 200k 301k 150k 100nf 100nf 22nf 22nf 100nf 220nf c tisp4180, tpa150a12 or tpb150b12 tisp5180, vdd 100k note: resistors must have 1% tolerance and capacitors have 20% tolerance unless otherwise specified. 5% 5% 5% 5% 5% 5% 5% 1n4003 1n4003 1n4003 1n4003 vdd 20% 1n914 : crystal is 3.579545mhz, 0.1% frequency tolerance. 1n914 1n914 1n914 1n914 r 3 r 2 : for bt application c=0.1 f 5%, r 3 =422k ? 1%, r 2 =422k ? 1% : for applications where cas speech immunity is required (e.g. cidcw) r 1 r 1 : r 1 = 430k, r 4 = 34k for v dd = 5v 10% (see figure 10) : r 1 = 620k, r 4 = 63k4 for v dd = 3v 10% (see figure 10) c=0.1 f 5%, r 3 =825k ? 1%, r 2 =226k ? 1% r 4 r 4
mt88e43b data sheet 14 zarlink semiconductor inc. figure 10 - gain ratio as a function of nominal vdd note: in the application circuits shown in figures 9 and 11, the gain ratio of mt88e43 opamp is gainratio 464k ? r 1 r 4 + ------------------ - =
mt88e43b data sheet 15 zarlink semiconductor inc. figure 11 - application circuit with improved common mode noise immunity and isolation in line interface a pprovals fcc part 68, doc cs-03, ul 1459, and can/csa-22.2 no. 225-m90 are all system (i.e. connectors, power supply, cabinet, etc.) requirements. since the mt88e43 is a component and no t a system, the application circuit (figure 11) has been designed to meet the co trunk inte rface requirements of fcc, doc, ul, and csa; thus enabling the complete system to be approved by these standards bodies. products are designed in accordance with meeting the abov e requirements; however, fu ll conformance to these standards is dependent upon the application in which the mt 88e43 is being used, and therefore, approvals are the responsibility of the customer and za rlink will not have tested the pr oduct to meet t he above standards. in+ in- gs v ref trigin trigrc trigout mode oscin oscout v ss v dd st/gt est std int dr data dclk fsken pwdn ic mt88e43 cap cd (fsk interface mode 0 selected) vdd = to microcontroller = from microcontroller 100nf tip / a ring / b vdd vdd 53k6 60k4 464k 12k1 464k 200k 150k 330nf 100nf 22nf 22nf 100nf 220nf vdd 100k vdd 10nf vdd note: resistors must have 1% tolerance, capacitors have 20% tolerance unless specified otherwise. motorola 4n25 1n4003 1n4003 1n4003 1n4003 5% 5% 10% 5% 5% 5% 5% 20% 1n914 1n5231b : bridge rectifier diodes are 1n914. 10% c r 3 r 2 r 1 r 1 : r 1 = 430k, r 4 = 34k for v dd = 5v 10% (see figure 10) : r 1 = 620k, r 4 = 63k4 for v dd = 3v 10% (see figure 10) r 4 r 4 : for bt application c=0.1 f 5%, r 3 =422k ? 1%, r 2 =422k ? 1% : for applications where cas speech immunity is required (e.g. cidcw) c=0.1 f 5%, r 3 =825k ? 1%, r 2 =226k ? 1%
mt88e43b data sheet 16 zarlink semiconductor inc. * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ** under normal operating conditions voltage on any pin except supplies can be minimum v ss -1v to maximum v dd +1v for an input current limited to less than 200 ? . ? typical figures are at 25 o c and are for design aid only: not guaranteed and not subject to production testing. absolute maximum ratings* - voltages are with respect to v ss unless otherwise stated. parameter symbol min. max. units 1 supply voltage with respect to v ss v dd -0.3 6 v 2 voltage on any pin other than supplies ** v pin v ss -0.3 v dd +0.3 v 3 current at any pin other than supplies i pin 10 ma 4 storage temperature t st -65 150 o c recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. ? max. units 1 power supplies v dd 2.7 - 5.5 v 2 clock frequency f osc 3.579545 mhz 3 tolerance on clock frequency ? fc -0.1 +0.1 % 4 operating temperature t op -40 85 o c dc electrical characteristics ? characteristics sym. min. typ. ? max. units test conditions 1 s u p p l y standby supply current i ddq 0.5 15 a ali inputs are v dd /v ss except for oscillator pins. no analog input. outputs unloaded. pwdn=v dd 2 operating supply current v dd = 5v 10% v dd = 3v 10% i dd 4.7 2.5 8 4.5 ma ma all inputs are v dd /v ss except for oscillator pins. no analog input. outputs unloaded. pwdn=v ss fsken=v dd 3 power consumption po 44 mw 4 trigin, trigrc , pwdn schmitt input high threshold v t+ 0.48*v dd 0.68*v dd v schmitt input low threshold v t- 0.28*v dd 0.48*v dd v 5 schmitt hysteresis v hys 0.2 v 6 dclk, mode, fsken cmos input high voltage v ih 0.7*v dd v dd v cmos input low voltage v il v ss 0.3*v dd v
mt88e43b data sheet 17 zarlink semiconductor inc. ? dc electrical characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 o c and are for design aid only: not guaranteed and not subject to production testing. 7 trigout , dclk, data, dr , cd , std, est, st/gt output high sourcing current i oh 0.8 ma v oh =0.9*v dd 8 trigout , dclk, data, dr , cd , std, est, st/gt trigrc , int output low sinking current i ol 2mav ol =0.1*v dd 9 in+, in-, trigin input current iin1 1 av in =v dd to v ss pwdn, dclk, mode, fsken iin2 10 av in =v dd to v ss 1 0 trigrc output high-impedance current ioz1 1 av out =v dd to v ss 11 int ioz2 10 a 1 2 st/gt ioz3 5 ? 1 3 v ref output voltage v ref 0.5v dd - 0.05 0.5v dd + 0.05 v no load 1 4 output resistance r ref 2k ? 1 5 st/gt comparator threshold voltage v tgt 0.5v dd - 0.05 0.5v dd + 0.05 v ac electrical characteristics ? - dual tone alert signal detection characteristic sym. min. typ. ? max. unit notes* 1 low tone frequency f l - 2130 - hz 2 high tone frequency f h - 2750 - hz 3 frequency deviation accept 1.1% - - range within which tones are accepted 4 frequency deviation reject 3.5% - - ranges outside of which tones are rejected 5 accept signal level per tone -40 -37.78 --2 0.22 dbv 1 dbm 2 see note 3 dc electrical characteristics ? (continued) characteristics sym. min. typ. ? max. units test conditions
mt88e43b data sheet 18 zarlink semiconductor inc. ac electrical characteristi cs - timing parameter measurement voltage levels 6 reject signal level per tone - - -46 -43.78 dbv dbm see note 3 7 positive and negative twist accept 7--db 3 8 signal to noise ratio snr tone 20 - - db 1,2 1. dbv = decibels above or below a reference voltage of 1vrms. signal level is per tone. 2. dbm = decibels above or below a reference power of 1mw into 600 ohms, 0 dbm = 0.7746vrms. signal level is per tone. 3. twist = 20 log (f h amplitude / f l amplitude). *notes: 1. both tones have the same amplitude. 2. band limited random noise 300-3400hz. measurement valid only when tone is present. 3. with gain setting as shown in figure 10. production tested at 3v 10%, 5v 10%. = ac electrical characteristics are over recommend ed operating conditions, unless otherwise stated. ?typical figures are at 25 o c and are for design aid only: not guaranteed and not subject to production testing characteristics sym level units notes 1 cmos threshold voltage v ct 0.5*v dd v 2 rise/fall threshold voltage high v hm 0.7*v dd v 3 rise/fall threshold voltage low v lm 0.3*v dd v ac electrical characteristics ? - dual tone alert signal detection characteristic sym. min. typ. ? max. unit notes*
mt88e43b data sheet 19 zarlink semiconductor inc. ? electrical characteristics are over recommended operating conditions, unless otherwise stated. *notes 1. both mark and space have the same amplitude. 2. band limited random noise (200-3400hz). present when fsk signal is present. note that the bt band is 300-3400hz, the bellcore band is 0-4khz. 3. production tested at v dd =3v 10%, 5v 10%. ? ac electrical characteristics are over recommended operating conditions, unless otherwise stated. ? typical figures are nominal values and are for design aid only: not guaranteed and not subject to production testing. *notes 1. refer to figures 1716 and 19 electrical characteristics ? - gain setting amplifier characteristics sym. min. max. units test conditions 1 input leakage current i in 1 av ss v in v dd 2 input resistance r in 10 m ? 3 input offset voltage v os 25 mv 4 power supply rejection ra tio psrr 40 db 1khz ripple on v dd 5 common mode rejection cmrr 40 db v cmmin v in v cmmax 6 dc open loop voltage gain a vol 30 db 7 unity gain bandwidth f c 0.3 mhz 8 output voltage swing v o 0.5 v dd -0.5 v pp load 50k ? 9 maximum capacitive load (gs) c l 100 pf 10 maximum resistive load (gs) r l 50 k ? 11 common mode range voltage v cm 1.0 v dd -1.0 v ac electrical characteristics ? - fsk detection characteristics sym. min. typ. ? max. units notes* 1 input detection level -40 -37.78 10.0 -8 -5.78 398.1 dbv 1 dbm 2 mvrms 1. dbv = decibels above or below a reference voltage of 1 vrms. 2. dbm = decibels above or below a reference power of 1mw into 600 ohms. 0 dbm = 0.7746 vrms. 1,3 2 transmission rate 1188 1200 1212 baud 3 input frequency detection bell 202 1 (mark) bell 202 0 (space) ccitt v.23 1 (mark) ccitt v.23 0 (space) 1188 2178 1280.5 2068.5 1200 2200 1300 2100 1212 2222 1319.5 2131.5 hz hz hz hz 4 signal to noise ratio snr fsk 20 db 1,2 ac electrical characteristics ? - dual tone alert signal timing characteristics sym min max units notes* 1 alert signal present detect time t dp 0.5 10 ms 1 2 alert signal absent detect time t da 0.1 8 ms 1
mt88e43b data sheet 20 zarlink semiconductor inc. ? ac electrical characteristics are over recommende d operating conditions unless otherwise stated. ? ac electrical characteristics are over recommende d operating conditions unless otherwise stated. ? typical figures are at 25 o c and are for design aid only: not guaranteed and not subject to production testing. *notes: 1. fsk input data at 1200 12 baud. 2. osc1 at 3.579545 mhz 0.1%. 3. function of signal condition. ? ac electrical characteristics are over recommende d operating conditions unless otherwise stated. ac electrical ch aracteristics ? - 3-wire interface timing characteristics sym. min. max. units notes 1 pwdn osc1 power-up time t pu 50 ms 2 power-down time t pd 1ms 3 cd input fsk to cd low delay t cp 25 ms 4 input fsk to cd high delay t ca 8ms 5hysteresis 8 ms ac electrical ch aracteristics ? - 3-wire interface timing (mode 0) characteristics sym. min. typ. ? max. units notes* 1 dr rise time t rr 200 ns into 50 pf load 2 fall time t rf 200 ns into 50 pf load 3 low time t rl 415 416 417 s2 4 data rate 1188 1200 1212 baud 1 5 input fsk to data delay t idd 15ms 6 data dclk rise time t r 200 ns into 50 pf load 7 fall time t f 200 ns into 50 pf load 8 data to dclk delay t dcd 6416 s1, 2, 3 9 dclk to data delay t cdd 6416 s1, 2, 3 10 dclk frequency f dclk0 1201.6 1202.8 1204 hz 2 11 high time t ch 415 416 417 s2 12 low time t cl 415 416 417 s2 13 dclk dr dclk to dr delay t crd 415 416 417 s2 ac electrical ch aracteristics ? - 3-wire interface timing (mode 1) characteristics sym. min. max. units notes 1 dclk frequency f dclk1 1mhz 2 duty cycle 30 70 % 3rise time t r1 20 ns 4 dclk, dr dclk low set up to dr t dds 500 ns 5 dclk low hold time after dr t ddh 500 ns
mt88e43b data sheet 21 zarlink semiconductor inc. figure 12 - data and dclk mode 0 output timing figure 13 - dr output timing data dclk t r t dcd t cdd t r t f t cl t ch t f v hm v lm v ct v hm v lm v ct t rf t rr t rl dr v hm v lm v ct
mt88e43b data sheet 22 zarlink semiconductor inc. figure 14 - serial data interface timing (mode 0) figure 15 - dclk mode 1 input timing figure 16 - serial data interface timing (mode 1) (a/b) data dclk dr stop start stop start stop start stop start b0 b1 b2 b3 b4 b5 b6 b7 b7 10 b0 b1 b2 b3 b4 b5 b6 b7 10 b0 b1 b2 10 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 stop start stop start t idd t crd 1/f dclk0 t rl tip/ring wires dclk t r1 v hm v lm stop start stop 0 1 234 5 67 7 word n word n+1 0 1 2 3 4 5 67 word n 0 word n-1 7 1/f dclk1 t rl t ddh 6 t dds demodulated dr dclk data internal bit stream 1 2 1 dclk clears dr 2 dclk does not clear dr , so dr is low for maximum time (1/2 bit width)
mt88e43b data sheet 23 zarlink semiconductor inc. figure 17 - input and output timing for bt caller display service (cds), e.g., clip notes: 1) the total recognition time is t rec = t gp + t dp , where t gp is the tone present guard time and t dp is the tone present detect time (refer to section ?dual tone detection guard time? on page 6 for details). v tgt is the comparator threshold (refer to figure 4). 2) the total tone absent time is t abs = t ga + t da , where t ga is the tone absent guard time and t da is the tone absent detect time (refer to section ?dual tone detection guard time? on page 6 for details). v tgt is the comparator threshold (refer to figure 4). 3) by choosing t ga =15ms, t abs will be 15-25 ms so that the curren t wetting pulse and ac load can be applied right after the std falling edge. 4) sin227 specifies that the ac and dc loads should be removed between 50-150 ms after the end of the fsk signal, indicated by cd returning to high. the mt88e43 may also be powered down at this time. 5) fsken should be set low when fsk is not expected to prevent the fsk demodulator from reacting to other in-band signals such a s speech, tone alert signal and dtmf tones. 6) trigout is the ring envelope during ringing. line reversal alerting signal ch. seizure mark data packet ring ..101010.. data t dp t da t gp t ga t rec t abs note 3 t cp t ca ab c d e f g zss (refer to sin227) < 0.5ma (optional) <120 a note 4 v tgt note 6 note 5 a/b wires trigout pwdn est st/gt std te dc load te ac load fsken cd dr dclk data oscout a 100ms b = 88-110ms c 45ms (up to 5sec) d = 80-262ms e = 45-75ms f 2.5sec (typ. 500ms) g > 200ms note: all values obtained from sin227 issue 1 note 1 note 2 50-150ms current wetting pulse (see sin227) t pu t pd 15 1ms 20 5ms
mt88e43b data sheet 24 zarlink semiconductor inc. figure 18 - input and output timing for cc a caller display serv ice (cds), e.g., clip notes: 1) tw/p&e/312 specifies that the ac and dc loads should be removed between 50 to 150 ms after the end of the fsk signal, indicate d by cd returning to high. the mt88e43 may also be powered down at this time. 2) fsken should be set low when fsk is not expected to prevent the fsk demodulator from reacting to other in-band signals such a s speech, and dtmf tones. 3) trigout represents the ring envelope during ringing. line reversal ring burst ch. seizure mark data packet first ring cycle ..101010.. data 250-400ms t cp t ca a bc d ef note 1 note 2 a/b wires trigout pwdn te dc load te ac load fsken cd dr dclk data oscout 50-150ms note 3 a = 200-450ms b 500ms c = 80-262ms d = 45-262ms e 2.5s (typ. 500ms) f >200ms note: parameter f from "cca exceptions document issue 3" note 3 t pu t pd
mt88e43b data sheet 25 zarlink semiconductor inc. figure 19 - input and output timing for bellco re on-hook data transmission associated with ringing, e.g., cid notes: this on-hook case application is included because a cidcw (off-hook) cpe should also be capable of receiving on-hook data transmission (with ringing) from the end office. tr-nwt-00057 5 specifies that cidcw will be offe red only to lines which subscri be to cid. 1) the cpe designer may choose to enable the mt88e43 only after t he end of ringing to conserve power in a battery operated cpe. cd is not activated by ringing. 2) the cpe designer may choose to set fsken always high while the cpe is on-hook. setting fsken low prevents the fsk demodulator from reacting to other in-band signals such as speech, cas or dtmf tones. 3) the microcontroller in the cpe powers down the mt88e43 after cd has become inactive. 4) the microcontroller times out if cd is not activated. 1st ring 2nd ring ch. seizure mark data packet a cdef .101010.. data note 1 note 2 note 3 note 1 note 4 t ca t cp b tip/ring trigout pwdn oscout fsken cd dr dclk data a = 2sec typical b = 250-500ms c = 250ms d = 150ms e = feature specific max c+d+e = 2.9 to 3.7sec f 200ms t pd t pu
mt88e43b data sheet 26 zarlink semiconductor inc. figure 20 - input and output timing for bellcore off-hook data transmission, e.g., cidcw notes : 1) in a cpe where ac power is not available, the designer may choose to switch over to line power when the cpe goes off-hook and use battery power while on-hook. the cpe should also be cid (on-hook) capable because tr-nwt-000575 specifies that cidcw will be offered only to lines which subscribe to cid. 2) non-fsk signals such as cas, speech and dtmf tone s are in the same frequen cy band as fsk. they will be demodulate d and give false data. the fsken pin should be set low to disable the fsk demodulator when fsk is not expected. 3) fsken may be set high as soon as the cpe has finished sending the acknowledgment signal ack. tr-nwt-000575 specifies that ack = dtmf d for non-adsi cpe, a for adsi cpe. 4) fsken should be set low when cd has become inactive. 5) in an unsuccessful attempt where the end office does not send the fsk signal, the cpe should unmute the handset and enable th e keypad after this interval. 6) sr-tsv-002476 states that it is desirable that the cpe have an on/off switch for the cas detector. see sw1 in figure 4. 7) the total recognition time is t rec = t gp + t dp , where t gp is the tone present guard time and t dp is the tone present detect time (refer to section ?dual tone detection guard time? on page 6 for details). v tgt is the comparator threshold (refer to figure 4). 8) the total tone absent time is t abs = t ga + t da , where t ga is the tone absent guard time and t da is the tone absent detect time (refer to section ?dual tone detection guard time? on page 6 for details). v tgt is the comparator threshold (refer to figure 4). cpe goes off-hook cas ack cpe sends cpe mutes handset & disables keypad mark data cpe unmutes handset and enables keypad t dp t da t gp t ga t rec t abs t cp t ca data v tgt ac e f g bd note 1 note 2 note 3 note 4 note 5 tip/ring pwdn fsken oscout est st/gt std (note 6) cd dr dclk data packet a = 75-85ms b = 0-100ms c = 55-65ms d = 0-500ms e = 58-75ms f = feature specific g 50ms note 7 note 8 t pu

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